1. Field of the Invention
The present invention relates to a high voltage metal-oxide-semiconductor (HVMOS) transistor, and more particularly, to a HVMOS transistor with improved channel hot carrier performance, and a related method of manufacturing the HVMOS transistor.
2. Description of the Prior Art
When a metal-oxide-semiconductor (MOS) transistor undergoes stress, an intense vertical electric field is created around a channel which transmits carriers from the source terminal to the drain terminal, causing some carriers in the channel to be forcibly injected into the gate terminal, resulting in damage to the Si/SiO2 interface. Please refer to FIG. 1, which is an exemplary diagram of a channel hot carrier in an N-type MOS transistor. The N-type MOS transistor includes a P well within a substrate SUB, a gate poly PO guarded by two spacers SP, and two carrier plus regions N+ located within N-type drain drift (NDD) regions NDD. When the N-type MOS transistor is activated to enter an on-state, a channel NC is built under the gate poly PO to connect drain and source terminals via the N+ regions and the NDD regions. If the bias voltage applied to the gate is raised to a value as high as the bias voltage at the drain terminal, the N-type MOS transistor is stressed. Under this circumstance, an intense electric field is built across the channel NC, and therefore certain hot carriers, i.e., carriers with huge energy, are forcibly injected into the gate poly PO and trapped inside a gate oxide layer, leading to permanent damage to the N-type MOS transistor, and the gate voltage cannot effectively control channel conduction as well.
For a conventional high voltage metal-oxide-semiconductor (HVMOS) transistor made by a high voltage (HV) process, the channel hot carrier may cause serious problems. For example, when an HVMOS transistor is operated under maximum operating voltage or stressed for a long time, the threshold thereof will drift and cause permanent damage. Please refer to FIG. 2, which is a diagram of a threshold voltage Vt variation of a conventional HVMOS transistor versus time when the conventional HVMOS transistor is operated under maximum operating voltage. Consider a case where the conventional HVMOS is operated with a maximum operating voltage of 20 V applied to both the gate and the drain terminals under a temperature of 140° C. It can be seen from the figure that the threshold voltage suffers from a serious variation—about 150% variation—after 24 hours.
Therefore, to fabricate more reliable semiconductor products, the channel hot carrier issue of an HVMOS transistor must be overcome so a stable threshold voltage can be sustained under any circumstance.